View OV5017_163761.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

OV5017
Features
n Single chip 1/4" video image sensor n Progressive scan n Built-in analog-to-digital (A/D) 8-bit pixel resolution n Programmable features n Frame rate of 50 ~ 0.5 frames per second (fps) n Exposure setting: 1 frame ~ 1/100 frame n Image size: 4.2 mm x 3.2 mm n AGC (auto gain control): 0 ~ 18 dB n Gamma correction: 0.45/1.0 n Pixel elements - 384 x 288 n External frame sync capability n Signal-to-noise (S/N) ratio > 42 dB n Minimum illumination of 0.5 lux at f1.4 at 50 fps n Single 5-volt supply operation for analog and 5/3.3 volts for digital n Power consumption
-- Active: less than 100 mW at 50 fps -- Standby: less than 100 A
Overview
The OV5017 is a black and white digital camera chip that uses OmniVision's CMOS image core technology. Combining the CMOS sensor technology and an easy to use digital interface, the OV5017 offers a low cost solution for high-quality video image applications. The digital video port supplies a continuous bytewide image data. On-chip programmable features include variable frame rate, exposure setting, and image size. All the camera features are register based, accessing the video data and configuring the chip is as easy as read/write of a static memory.
AGND VRCR FSI AVDD SVDD SGND AVO VVDD AO DEVDD DEGND ZGND AGND N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C A3 6 5 4 3 2 1 48 47 46 45 44 43 7 8 9 10 11 12 13 14 15 16 17 18 42 41 40 39 38 37 36 35 34 33 32 31
n Pixel dimension of 11 um x 11 um
OV5017
n 48-pin package
VR2 ZVDD OVDD D7 D6 D5 D4 D3 D2 D1 D0 OGND
OV5017 PIN ASSIGNMENTS
OmniVision Technologies, Inc. reserves the right to make changes without further notice to any product herein to improve reliability, function, or design. OmniVision Technologies, Inc. does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. No part of this publication may be copied or reproduced, in any form without the prior written consent of OmniVision Technologies, Inc.
Distributed by :COMedia Ltd, Rm802, Nan Fung tr, Castle Peak Rd, Tsuen Wan, NT, Hong Kong Tel: (852) 2498 6248 Fax: (852)2414 3050
A2 A1 OEB WEB CSB XCLKI XCLKO HREF PCLK VSYNC DVDD DGND
19 20 21 22 23 24 25 26 27 28 29 30
Version 1.6, October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
The Image Core is a complete analog video camera with 384 x 288 pixel size, which can run at full video speed. The analog video signal complies with CCIR standards. At 50 fps, it may be too fast for many applications; therefore, the frame rate or pixel rate can be programmed to match the external system requirements. The on-chip 8-bit A/D can convert the video signal at 50 fps, and the conversion is synchronized with the actual pixel rate. The OV5017 also outputs standard timing reference signals such as VSYNC, HREF, PCLK. Databus is shared by negating OEB. The exposure control can be set to auto or manual operation. Automatic exposure computation is based on full size image array and an exposure range over 100X. The AGC operation is tied to AEC in auto operation. Therefore, use automatic exposure control when selecting full image size. Manual exposure control allows individually adjusting exposure and gain based on actual application. Therefore, use manual exposure time if the window is smaller than full size or if the target object is brighter or darker than the average background. The frame rate divider can achieve various frame rates on the fly without changing the input clock frequency. Single frame operation provides one frame data transfer by controlling the assertion of HREF for one complete frame period. Setting FCTL(7) signals the control to assert the HREF in the next frame. Clearing this bit before the new frame cancels the assertion of HREF.
Table 1.Pin Descriptions
Pin #
1 2 3 4
Class
Bias Bias Bias I-0
Pin Name
SGND SVDD AVDD FSI
Description
Sensor ground. Connect to supply common. Sensor power (+5V) connection. Analog power (+5V) connection. External frame sync input. A rising edge on FSI sets the chip vertical sync timing. For proper operation, the frequency of FSI must be half of the programmed frame rate. Internally pulled down with a 100k resistor. Leave open or ground if unused. Internal reference voltage. Requires a 0.1uF external capacitor to AGND. Analog ground. Connect to supply common. Analog ground. Connect to supply common. Factory test. Leave open. Address inputs for internal the registers. Requires CSB = 0 to access the registers. Output enable for the eight bit data bus. OEB = 0 enables the data bus drivers. OEB = 1 puts the data bus in tristate.
5 6 7 8-17 18, 19, 20, 46 21
Bias Bias Bias FT I I
VrCR AGND AGND N/C A3-A0 OEB
2
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
Table 1.Pin Descriptions (Continued)
Pin #
22
Class
I
Pin Name
WEB
Description
Write enable input for the internal registers. When the chip is selected (CSB = 0), external data is latched into the registers with the rising edge of WEB. Chip select for the device. CSB = 0 selects the device. Crystal oscillator in/out pins. Nominal clock frequency is 14.31MHz for CCIR 50 Hz timing. The maximum pixel rate is limited to one half of the clock frequency. To connect an external clock to XCLKI, leave XCLKO open. Horizontal timing reference output. Asserted high during every valid line for the duration of the valid window width. The window sizing function affects the number of valid lines in a frame as well as the number of valid pixels in a line. HREF and status(1), are identical valid pixel timing information. Pixel clock output. Defaulted to be a continuous clock. Can be programmed via the internal register to be on during the valid pixel window only. Video data at output bus (D0-D7) is updated with the rising edge of PCLK and is guaranteed to be valid at the falling edge of PCLK. Vertical timing reference output. It is high once per frame for the duration of the vertical sync period. VSYNC and status (2) are identical vertical sync timing information. Digital power (+5V) connection. Digital ground. Connect to supply common Digital output ground. Connect to supply common Bi-directional data bus for video output data and internal register read/write operations. Digital output power (+5V/+3.3V) connection. Analog power (+5V) connection. Internal reference voltage. Requires a 0.1uF external capacitor to AGND. Analog ground. Connect to supply common. Decoder ground. Connect to supply common. Decoder power (+5V) connection. Video output power (+5V) connection. Composite video output. It is capable of driving 150 load, Vp-p is 2.0 V.
23 24, 25
I OD
CSB XCLKI, XCLKO
26
OD
HREF
27
OD
PCLK
28
OD
VSYNC
29 30 31 32-39
Bias Bias Bias OD
DVDD DGND OGND D0-D7
40 41 42 43 44 45 47 48
Bias Bias Bias Bias Bias Bias Bias Q
OVDD ZVDD VR2 ZGND DEGND DEVDD VVDD AVO
Pin Type and Default Level: I: digital input, floating, I-1: digital input, with 100k pull up, I-0: digital input, with 100k pull down, OD: digital CMOS level output, OA: analog CMOS, level output, XI/XO: xtal IO, K: analog input, Q: 75 output, FT: factory test, Bias: power supply bias
October 20, 1997
Version 1.6
3
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
1. Video Data Bus
HREF PROGRAMMED HORIZONTAL WINDOW WIDTH
A[3:0]
VIDEO PORT ADDRESS
CSB
OEB
PCLK
DATA[7:0]
VD
VD
VD
VD
VD
PIXEL DATA
Figure 1. Video Data Timing Showing Continuous Pixel Reading The eight bit video data from the A/D converter is synchronous to PCLK. The lowest level is `h00' and the highest is `hff', no reserved code for blanking or sync.
PCLK is the pixel clock that is either continuously on or present only during valid pixel window. If the continuous clock is used, HREF is often used to qualify the pixel data. HREF is asserted during the programmed horizontal and vertical window region. Video data is updated at the rising edge of PCLK and can be latched at the falling edge of PCLK.
As shown in Figure 1, reading of the video data is not different from reading other on-chip registers, it requires the assertion of OEB and CSB and the correct address. To maintain uninterrupted video data stream, OV5017 video data will be updated at each pixel clock as long as the OEB, CSB, and correct address are asserted as shown in Figure 1. Since the video data is continuous during the active window, to prevent new data overruns the previous one, the host has to make sure at least one video data is read in every pixel clock period. The status register bit RDY and OV allows host to perform polling and error detection.
1.1 Register Control
The register read/write is the same as normal memory access, using pins DATA[7:0], A[3:0], WEB, OEB, and CSB. As shown in Figure 2 and Figure 3, the read cycle can be chip select controlled or address controlled. The write cycle also can be chip select controlled or write enable controlled. The memory cycle is fully asynchronous to the frame or pixel timing. Write cycle affects only the registers which are writable, it does not affect read only registers such as video port status register. Since writing to certain
4
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
registers affects the basic camera operation, care must be taken when write occurs during the middle of active window. These effects are described in the individual register section. As a guide line, registers affects the frame rate, exposure time, window size, are better updated during the vertical sync .
CSB OEB
WEB
A[3:0]
ADD0
ADDN
DATA[7:0]
DATA0 READ CYCLE (CS CONTROLLED)
DATAN READ CYCLE (ADDRESS CONTROLLED)
Figure 2. Register Access Showing a Single Byte Read
OEB CSB
WEB
A[3:0]
ADD0
ADDN
DATA[7:0]
DATA0
DATAN
WRITE CYCLE (CS CONTROLLED)
WRITE CYCLE (WE CONTROLLED)
Figure 3. Register Access Showing Single Byte Write
October 20, 1997
Version 1.6
5
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
2. Registers
Table 2. Register Sets
A[3:0]
10xx 0000 0001
Register Name
VPORT STATUS FCTL
R/W
R R W
Bit Name
VD[7:0] TO2,TO1, , ,OV, VSYNC, HREF, RDY SFR, FSET, , , SKIP, FBLC, STOP, SRST AUTO, EX[6:0] GN[2:0] FDIV[5:0] GAMMA, MIR, DN, BKL, FZEX, PCKS, PCKI, BPSHP HWS[3:0], HWE[3:0] VWS[3:0], VWE[3:0] TST[7:0] TOPT[7:0]
Function
Video data Status register Single frame flow control system control Auto or manual exposure value Gain value Frame rate divider Miscellaneous controls
Default Value
xxxxxxxx 00xxxxxx 00xx0000
0010 0011 0100 0101
EXCTL GCTL FRCTL MCTL
R/W R/W R/W R/W
11111111 xxxxx000 xx000000 00000000
0110 0111 1110 1111
HWCTL VWCTL TST TOPT
R/W R/W W W
Window control Window control Reserved for test Reserved for test
00000000 00000000 xxxxxxxx xxxxxxxx
Note: Unimplemented bits in all the R/W registers return "0" in the read cycle, no effect in the write cycle.
2.1 Detailed Register Descriptions
The following table describes the function of each bit within a register: Table 3. Bit descriptions
Register Name
VPORT
Bit name
VD
Range
VD[7:0]
Function
This register selects the video data port. The video data is not latched in this VPORT, as long as VPORT remains selected. The video data is updated as new pixel signals are converted. Reserved bit.
STATUS
TO2
STA7
6
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017 Table 3. Bit descriptions (Continued)
Register Name Bit name
TO1 OV VSYNC HREF RDY
Confidential Preliminary Product Specification
Range
STA6 STA3 STA2 STA1 STA0 Reserved bit.
Function
Pixel data overrun flag. It is set each time pixel data is updated if STA0 has been set already. Reading of this register clears the bit. This bit duplicates the signal at pin VSYNC. This bit duplicates the signal at pin HREF. This bit is set each time pixel data is updated, and is cleared by reading the VPORT register. This bit will not be set if the VPORT register is being read while pixel data is updating. Set to initiate single frame transfer. This bit works only if FCTL[6] is also set. If this bit is set in the middle of a frame, HREF will not be asserted until the next new frame. This bit is cleared automatically at the end of the new frame so that it can be set again. Set to enable single frame operation mode. Since the video data is a continuous non-stop byte stream, the validity of the data is qualified only by assertion of HREF. In a continuous frame operation, HREF is asserted in every frame. In a single frame operation, HREF is asserted only for the first frame immediately after setting the FCTL[7]. The actual duration of HREF assertion is programmed by the window size. Makes VSYNC and HREF to skip every other frame. This function does not alter the pixel rate; it simply blocks their assertion in every other frame. Chooses how frequent the black level calibration is performed internally. It is set once every frame and cleared once every line. Line BLC can set the BLC within a fraction of a frame time. This is useful to speed up BLC process after power up or activation after standby mode. However, frame BLC provides better image stability. Set to stop chip clock and enter low power standby mode. This function does not alter register content. The chip is put in default state and all image data is lost. Setting this bit does not prevent further register access. Upon clearing this bit, it generally takes about two frames for the chip to become stable. Software reset enable. Setting this bit resets all the on-chip registers and puts the chip in default state. Upon clearing this bit, it generally takes about two frames for the chip to become stable.
FCTL
FSET
FCTL[7]
SFR
FCTL[6]
SKIP
FCTL[3]
FBLC
FCTL[2]
STOP
FCTL[1]
SRST
FCTL[0]
October 20, 1997
Version 1.6
7
OMNIVISION TECHNOLOGIES, Inc. OV5017 Table 3. Bit descriptions (Continued)
Register Name
EXCTL
Confidential Preliminary Product Specification
Bit name
AUTO EX
Range
EXCTL[7] EXCTL[6:0]
Function
Enables auto exposure. To select auto exposure mode, set this bit. To select manual exposure mode, clear this bit. Sets the exposure time, where 7fh is the 1/50s, and 00h is the 1/ (50*128*2)s. This register is used in manual exposure mode only. After updates are made to this register, it takes two frames for the chip to become stable. Selects the post amplifier gain, where 111 is the 18dB gain and 000 is the 0dB in a linear relationship. This register is used in manual exposure mode only. After updates are made to this register, it takes two frames for the chip to become stable. Divides the frame rate by 1 to 64 in steps of 1 by using this formula: Frame Rate = F0 / (FDIV+1) Pixel Rate = fosc / [(FDIV +1)*2] where fosc is the main clock frequency of XCLKi F0 = fosc / (458*625); F0=50 @ 14.318Mhz After updates are made to this register, it takes two frames for the chip to become stable.
GCTL
GN
GCTL[2:0]
FRCTL
FDIV
FRCTL[5:0]
MCTL
GAMA MIR NSR BKL FZEX PCKS PCKI BPSHP
MCTL[7] MCTL[6] MCTL[5] MCTL[4] MCTL[3] MCTL[2] MCTL[1] MCTL[0] HWCTL[7:4] HWCTL[3:0] VWCTL[7:4] VWCTL[3:0]
Set this bit to select gamma = 0.45, and clear this bit for gamma = 1. Set this bit to select mirror image. Set this bit to turn on indoor mode, and clear for outdoor mode. Set this bit to turn on backlight compensation. Set this bit to freeze the exposure setting. This works in auto exposure mode; it has no effect in manual exposure mode. Clear this bit to output continuous pixel clock to PCLK; set to output pixel clock only during the valid pixel window Set this bit to inverse the polarity of PCLK. Set this bit to disable sharpness function. Selects the start of the horizontal window. Selects the end of the horizontal window. Selects the start of the vertical window. Selects the end of the vertical window.
HWCTL/ VWCTL
HWS HWE VWS VWE
8
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017 Table 3. Bit descriptions (Continued)
Register Name Bit name Range
Confidential Preliminary Product Specification
Function
The array is divided into 16x16 blocks as shown in Figure 1.1. each block is H24xV18 pixels. The method for selecting vertical and horizontal window region is the same. Each direction uses an eight-bit register. Bit [7:4] selects the start block location. Bit [3:0] selects the end block location. For example, to select the shaded area as the active region, use HWCTL=4cH,VWCTL=44H. This window selection feature changes only the assertion time of HREF and does not change the pixel rate or the data rate. If the end location is equal to or less than the start location, the window size is from start location to the end of the right most edge.
VSYNC
HREF HWS 01 2 3 01 2 3 7 11 15 VWE - 24 X18 PIXELS 7 HWE 11 15
VWS
Figure 4. Windowing
October 20, 1997
Version 1.6
9
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
3. Electrical Specifications
This section provides the electrical parameters descriptions and timing diagrams.
3.1 Electrical Parameters
Table 4. Electrical parameters (0oC < TA < 85oC, voltages referenced to GND)
Symbol
Supply VDD1 VDD2 IDD1 IDD2 Inputs VIL VIH Cin tr, tr Input voltage LOW Input voltage HIGH Input capacitor Digital input rise/fall time 0.8 10 25 2.0 V V pF ns Supply voltage (digital/analog: DEVDD, ZVDD, AVDD, SVDD, VVDD, DVDD) Supply voltage (OVDD) 5.25 5.0 4.75 V
Descriptions
Max
Type
Min
Units
5.5 3.6
40 100
5.0 3.3
-
4.5 3.0
-
V V
mA uA
Supply Current (@ 50fps, 50pf CMOS load on data bus) Standby supply current
Outputs - standard load 25pf, 1.2k to 3.0volts VOH VOL Output voltage HIGH Output voltage LOW 0.6 2.4 V V
Clock input / Crystal Oscillator fosc Resonator frequency Load capacitor Parallel resistance Clock input rise/fall time Duty cycle if external clock input Video timing tPCLK tPHD tPDD PCLK cycle time (@ 50Hz fps) PCLK to HREF delay PCLK to DATA delay 25 25 139 ns ns ns 5 60 14.31818 10 1M 25 40 MHz pF
W
ns %
10
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
Table 4. Electrical parameters (0oC < TA < 85oC, voltages referenced to GND) (Continued)
Symbol
Interface timing
Descriptions
Max
Type
Min
Units
tOE tOEZ tRC tCS tCSA tCSX tAA tAX tWC tWE tAS tAH tDS tDH tSYNC tPD
Output enable access time Output enable to Z delay Register read cycle time Chip select pulse width Chip select access time Chip select to data invalid time Address access time Address data invalid time Register write cycle time Write enable pulse width Write cycle address set up time Write cycle address hold time Write cycle data set up time Write cycle data hold time External FSI cycle time Chip power up time
15 15 30 15 30 15 100
-
100 50
ns ns ns ns ns ns ns
2 100 50 0 0 20 0 -
ns ns ns ns ns ns ns frame us
DIGIAL/Analog video parameters AVO Composite video level (p-p) sync amplitude Output load resistance horizontal line width horizontal sync width horizontal blank front porch horizontal blank back porch active pixel in one scan line 0.55 2.0 150 458 32 9 33 384 0.6 V
AVSYNC
Ravo
V Ohm pclk pclk pclk pclk pclk
tH tHSYNC tHF tHB tHACT
October 20, 1997
Version 1.6
11
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
Table 4. Electrical parameters (0oC < TA < 85oC, voltages referenced to GND) (Continued)
Symbol tVB1 tV tVSYNC tVF1 tVB1 tVF2 tVB2 tVACT Descriptions
field 2 vertica back equaliztion width vertical field width vertical sync width field 1 vertical front equlization width field 1 vertica back equaliztion width field 2 vertical front equlization width field 2 vertica back equaliztion width active line in a field
Max
Type
312.5 2.5 3 19 2.5 19.5 288
Min
Units tH tH tH tH tH tH tH tH
12
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
3.2 Timing diagrams
2
2
1
1
H00
288
Y383
288
287
287
Y382
0
0
0
0
H00
0
(A) HORIZONTAL TIMING
Y1
Y0
288
H00
288
287
INTERNAL H-SYNC
VSYNC
XCLKI
HREF
DATA[7:0]
HREF
PCLK
287
Figure 5. Video Data Timing (384 x 288), PCLK = 1/4 XCLKi
October 20, 1997
Version 1.6
DATA[7:0]
0
H00
(B) VERTICAL TIMING
3
3
2
2
1
1
0
0
13
OMNIVISION TECHNOLOGIES, Inc.
14
H00 H00 Y0 Y1 Y190 Y191 (A) HORIZONTAL TIMING 215 288 1 216 73 74 75 215 216 288 1 37 38 144 1 2 3 143 144 1 2 0 H00 0 0 0 0 0 0 H00 0
OV5017
XCLKI
PCLK
HREF
DATA[7:0]
Figure 6. Video Port Timing (192 x 144), PCLK = 1/2 XCLKi
Version 1.6
(B) VERTICAL TIMING
VSYNC
INTERNAL H-SYNC
143
HREF
DATA[7:0]
Confidential Preliminary Product Specification
October 20, 1997
OV5017
October 20, 1997
H00 H00 Y0 Y1 Y382 Y383 (A) HORIZONTAL TIMING 288 1 2 3 287 288 1 2 288 1 2 3 287 288 1 2 0 H00 0 0 0 0 0 0 H00 0 (B) VERTICAL TIMING
XCLKI
PCLK
OMNIVISION TECHNOLOGIES, Inc.
HREF
DATA[7:0]
Version 1.6
VSYNC
INTERNAL H-SYNC
287
HREF
287
DATA[7:0]
Confidential Preliminary Product Specification
15
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
Figure 7. Video Port Timing (384 x 288), PCLK = 1/2 XCLKi
TPCLK
TPHD
TPHD
HREF
PCLK
TPDD
Figure 8. Pixel Timing
16
Version 1.6
DATA[7:0]
October 20, 1997
OV5017
OEB TRC
October 20, 1997
TRC ADD0 TCSA TCSX TAA TOEZ ADDN TOE DATA0 DATAN TAX READ CYCLE TWC TCS CSB TWE OEB WEB TAS ADD0 TAH TAS ADDN TAH DATA0 TDS TDH DATAN TDS TDH WRITE CYCLE
CSB
WEB
OMNIVISION TECHNOLOGIES, Inc.
A[3:0]
DATA[7:0]
Figure 9. Register R/W Timing
Version 1.6
A[3:0]
DATA[7:0]
Confidential Preliminary Product Specification
17
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
1
DIE
Package Center (0, 0) Array Center (-0.030, -0.017)
SENSOR ARRAY
Top View
Figure 10. OV5017 Sensor Array Location Dimensions (in inches)
18
Version 1.6
October 20, 1997
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
0.440 0.005 31 0.040 0.003 42
+0.010 0.060 -0.005 TYP. 0.040 0.007 TYP. 43
30
NOTES: 1) All dimensions in inches
48
0.020 0.003 TYP. 19 6
R 0.0075 18 4 CORNERS
R 0.0075 48 PLCS 0.003 0.065 0.007 0.002
7
0.085 0.010
0.003
0.030 0.003 0.015 0.002 0.020 0.002 0.036 MIN. 42
+0.012 0.560 SQ. -0.005 0.430 SQ. 0.005 0.350 SQ. 0.005
31 31 30
43 43
42
30
48 1
6
6 7 7 0.006 MAX. 0.002 TYP. 18
19
19
18
Figure 11. OV5017 Package Outline Dimensions
October 20, 1997
Version 1.6
19
OMNIVISION TECHNOLOGIES, Inc. OV5017
Confidential Preliminary Product Specification
ERRATA
11/20/97 1. In default mode, the video data changes on the falling edge of PCLK instead of on the rising edge. We recommand inverting the PCLK pin polarity by setting MCTL(1) so the video data can still be latched on the falling edge of PCLK. All the pclk timing parameters is applied to inverted PCLK. 2. OV5017 default active HREF window width has one extra pixel, 385 instead of 384, the back porch blanking is one less, that is: tHACT = 385, tHB = 32. 2/14/98 3. A glitch ( width 1/2 ~ 10 PCLKS) in HREF appears between VSYNC and the first valid HREF if programmed FRCTL(5:0) >= 9. 4. Intensity of lines (32,33,256,257) may be different from the rest of image if programmed FRCTL(5:0)= 4,5,9~11,13~15,17~22,24~63.
20
Version 1.6
October 20, 1997

▲Up To Search▲

Price & Availability of OV5017

	To Download OV5017 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .